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EM250
Table 20. Configuration Table for the UART Module
SC1_UARTCFG
GPIO Pin Function
1
1
1
0
1
1
-
-
0
-
-
0/
SC1-2 mode
SC1-2 mode
SC1-4A mode
TXD/RXD output/input
Illegal
TXD/RXD/nCTS output/input/input
1
nRTS output = ON/OFF
1
1
1
-
SC1-4A mode
TXD/RXD/nCTS output/input/input
nRTS output = ON if 2 or more bytes will fit in receive buffer
1
1
1
0
0
-
1
0
-
-
-
-
SC1-4A mode
SC1-4A mode
SC1-3M mode
Reserved
Illegal
Illegal
Characters transmitted and received are passed through transmit and receive FIFOs. The transmit and receive
FIFOs are 4 bytes deep. The FIFOs are accessed under software control by accessing the SC1_DATA data
register or under hardware control by the SC1 DMA.
When a transmit character is written to the (empty) transmit FIFO, the register bit SC1_UARTTXIDLE in the
SC1_UARTSTAT register clears to indicate that not all characters are transmitted yet. Further transmit
characters can be written to the transmit FIFO until it is full, which causes the register bit SC1_UARTTXFREE
in the SC1_UARTSTAT register to clear. After shifting one transmit character to the TXD pin, space for one
transmit character becomes available in the transmit FIFO. This causes the register bit SC1_UARTTXFREE in
the SC1_UARTSTAT register to get set. After all characters are shifted out, the transmit FIFO empties, which
causes the register bit SC1_UARTTXIDLE in the SC1_UARTSTAT register to get set.
A received character is stored with its parity and frame error status in the receive FIFO. The register bit
SC1_UARTRXVAL in the SC1_UARTSTAT register is set to indicate that not all received characters are read out
from the receive FIFO. The error status of a received byte is available with the register bits SC1_UARTPARERR
and SC1_UARTFRMERR in the SC1_UARTSTAT register. When the DMA controller is transferring the data from
the receive FIFO to a memory buffer, it checks the stored parity and frame error status flags. When an error is
flagged, the SC1_RXERRA/B register is updated, marking the offset to the first received character with parity
or frame error.
When the 4-character receive FIFO contains 3 characters, flow control needs to be used to avoid an overflow
event. One method is to use software handshaking by transmitting reserved XON/XOFF characters which are
interpreted by the transmitting terminal to pause further transmissions (to the receive FIFO). Another method
is to use hardware handshaking using XOFF assertion through the nRTS signal.
There are two schemes available to assert the nRTS signal. The first scheme is to initiate nRTS assertion with
software by setting the register bit SC1_UARTRTS in the SC1_UARTCFG register. The second scheme is to
assert nRTS automatically depending on the fill state of the receive FIFO. This is enabled with the register bit
SC1_UARTAUTO in the SC1_UARTCFG register.
The UART also contains overrun protection for both the FIFO and DMA options. If the transmitting terminal
continues to transmit characters to the receive FIFO, only 4 characters are stored in the FIFO. Additional
characters are dropped, and the register bit SC1_UARTRXOVF in the SC1_UARTSTAT register is set. Should this
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120-0082-000V Rev 1.1
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